3D architectures or 3D chip stacks (sometimes referred to herein as “3D stack”, “3D IC”, “stack of dies”) encompass architectures where chips are positioned on more than one plane and may be integrated both horizontally and vertically into a single circuit, such as a system on a chip. Additionally, 3D ICs also encompass the situation where there exists more than one vertical stack of chips in the circuit. Furthermore, the chips in a 3D IC may be of different varieties, such as, but not limited to, processors, memory (of various types and capacities), digital signal processors (“DSP”), radio frequency (“RF”) modules, etc., as would be familiar to those of skill in the art.
A typical current 3D IC verification methodology system is shown as system 100 in FIG. 1 which illustrates a simplified schematic diagram of a prior art 3D IC verification methodology system. Four individual dies, Die A 102, Die B 103, Die C 104, and Die D 105 are stacked in a 3D IC stack and the stack is operatively connected to a test bench 101 such that only Die A is directly connected to the test bench and each of the other dies in the stack, which are separated by inter-die interfaces 107, 108, and 109, respectively as shown, are not directly connected to the test bench. Peripheral drivers 106, as are known in the art, are also attached to the test bench 101. The interactions between Dies A through D are shown by arrows 1A, 1B, 1C, 1D, 2B, 2C, 2D, 3C, 3D, and 4D.
In order to perform functional verification of Die A 102 using the test bench 101 and the peripheral drivers 106, the interactions between all of the dies in the stack must be taken into account thereby requiring that the functionality of the 3D IC be verified as one interconnected system. Thus, verifying Die A 102 requires including the test bench 101 (and thus peripheral drivers 106) via interaction 1A, Die B via interaction 2B, Die C via interaction 2C, and Die D via interaction 2D. Similarly, verifying Die C 104 requires including the test bench 101 (and thus peripheral drivers 106) via interaction 1C, Die A via interaction 2C, Die B via interaction 3C, and die D via interaction 4D. Similar verification requirements exist for Dies B and D. Furthermore, the typical current 3D IC verification methodology is limited to verification at the signal level.